Index: include/avr/iomxx0_1.h
===================================================================
RCS file: /sources/avr-libc/avr-libc/include/avr/iomxx0_1.h,v
retrieving revision 1.12
diff -u -r1.12 iomxx0_1.h
--- include/avr/iomxx0_1.h	12 Dec 2007 14:00:49 -0000	1.12
+++ include/avr/iomxx0_1.h	28 Apr 2009 12:58:53 -0000
@@ -1,4 +1,5 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
+/* Copyright (c) 2005 Anatoly Sokolov
+   Copyright (c) 2009, Frédéric Nadeau
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -46,7 +47,7 @@
 #  define _AVR_IOXXX_H_ "iomxx0_1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
 # define __ATmegaxx0__
@@ -299,7 +300,7 @@
 #define TOV5    0
 
 #define PCIFR   _SFR_IO8(0x1B)
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 # define PCIF2  2
 #endif /* __ATmegaxx0__ */
 #define PCIF1   1
@@ -322,7 +323,7 @@
 #define INT4    4
 #define INT3    3
 #define INT2    2
-#define INT1    1 
+#define INT1    1
 #define INT0    0
 
 #define GPIOR0  _SFR_IO8(0x1E)
@@ -556,7 +557,7 @@
 #define PCINT9  1
 #define PCINT8  0
 
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 # define PCMSK2 _SFR_MEM8(0x6D)
 # define PCINT23 7
 # define PCINT22 6
@@ -1251,7 +1252,7 @@
 
 /* Reserved [0x12E..0x12F] */
 
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 
 # define UCSR3A _SFR_MEM8(0x130)
 # define RXC3   7
@@ -1300,211 +1301,261 @@
 /* Interrupt vectors */
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
+#define INT0_vect_num 			1
 #define INT0_vect			_VECTOR(1)
 #define SIG_INTERRUPT0			_VECTOR(1)
 
 /* External Interrupt Request 1 */
+#define INT1_vect_num 			2
 #define INT1_vect			_VECTOR(2)
 #define SIG_INTERRUPT1			_VECTOR(2)
 
 /* External Interrupt Request 2 */
+#define INT2_vect_num 			3
 #define INT2_vect			_VECTOR(3)
 #define SIG_INTERRUPT2			_VECTOR(3)
 
 /* External Interrupt Request 3 */
+#define INT3_vect_num 			4
 #define INT3_vect			_VECTOR(4)
 #define SIG_INTERRUPT3			_VECTOR(4)
 
 /* External Interrupt Request 4 */
+#define INT4_vect_num 			5
 #define INT4_vect			_VECTOR(5)
 #define SIG_INTERRUPT4			_VECTOR(5)
 
 /* External Interrupt Request 5 */
+#define INT5_vect_num 			6
 #define INT5_vect			_VECTOR(6)
 #define SIG_INTERRUPT5			_VECTOR(6)
 
 /* External Interrupt Request 6 */
+#define INT6_vect_num 			7
 #define INT6_vect			_VECTOR(7)
 #define SIG_INTERRUPT6			_VECTOR(7)
 
 /* External Interrupt Request 7 */
+#define INT7_vect_num 			8
 #define INT7_vect			_VECTOR(8)
 #define SIG_INTERRUPT7			_VECTOR(8)
 
 /* Pin Change Interrupt Request 0 */
+#define PCINT0_vect_num 			9
 #define PCINT0_vect			_VECTOR(9)
 #define SIG_PIN_CHANGE0			_VECTOR(9)
 
 /* Pin Change Interrupt Request 1 */
+#define PCINT1_vect_num 			10
 #define PCINT1_vect			_VECTOR(10)
 #define SIG_PIN_CHANGE1			_VECTOR(10)
 
 #if defined(__ATmegaxx0__)
 /* Pin Change Interrupt Request 2 */
+#define PCINT2_vect_num 			11
 #define PCINT2_vect			_VECTOR(11)
 #define SIG_PIN_CHANGE2			_VECTOR(11)
 
 #endif /* __ATmegaxx0__ */
 
 /* Watchdog Time-out Interrupt */
+#define WDT_vect_num 			12
 #define WDT_vect			_VECTOR(12)
 #define SIG_WATCHDOG_TIMEOUT		_VECTOR(12)
 
 /* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPA_vect_num 		13
 #define TIMER2_COMPA_vect		_VECTOR(13)
 #define SIG_OUTPUT_COMPARE2A		_VECTOR(13)
 
 /* Timer/Counter2 Compare Match B */
+#define TIMER2_COMPB_vect_num 		14
 #define TIMER2_COMPB_vect		_VECTOR(14)
 #define SIG_OUTPUT_COMPARE2B		_VECTOR(14)
 
 /* Timer/Counter2 Overflow */
+#define TIMER2_OVF_vect_num 			15
 #define TIMER2_OVF_vect			_VECTOR(15)
 #define SIG_OVERFLOW2			_VECTOR(15)
 
 /* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect_num 		16
 #define TIMER1_CAPT_vect		_VECTOR(16)
 #define SIG_INPUT_CAPTURE1		_VECTOR(16)
 
 /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect_num 		17
 #define TIMER1_COMPA_vect		_VECTOR(17)
 #define SIG_OUTPUT_COMPARE1A		_VECTOR(17)
 
 /* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect_num 		18
 #define TIMER1_COMPB_vect		_VECTOR(18)
 #define SIG_OUTPUT_COMPARE1B		_VECTOR(18)
 
 /* Timer/Counter1 Compare Match C */
+#define TIMER1_COMPC_vect_num 		19
 #define TIMER1_COMPC_vect		_VECTOR(19)
 #define SIG_OUTPUT_COMPARE1C		_VECTOR(19)
 
 /* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect_num 			20
 #define TIMER1_OVF_vect			_VECTOR(20)
 #define SIG_OVERFLOW1			_VECTOR(20)
 
 /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect_num 		21
 #define TIMER0_COMPA_vect		_VECTOR(21)
 #define SIG_OUTPUT_COMPARE0A		_VECTOR(21)
 
 /* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect_num 		22
 #define TIMER0_COMPB_vect		_VECTOR(22)
 #define SIG_OUTPUT_COMPARE0B		_VECTOR(22)
 
 /* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect_num 			23
 #define TIMER0_OVF_vect			_VECTOR(23)
 #define SIG_OVERFLOW0			_VECTOR(23)
 
 /* SPI Serial Transfer Complete */
+#define SPI_STC_vect_num 			24
 #define SPI_STC_vect			_VECTOR(24)
 #define SIG_SPI				_VECTOR(24)
 
 /* USART0, Rx Complete */
+#define USART0_RX_vect_num 			25
 #define USART0_RX_vect			_VECTOR(25)
 #define SIG_USART0_RECV			_VECTOR(25)
 
 /* USART0 Data register Empty */
+#define USART0_UDRE_vect_num 		26
 #define USART0_UDRE_vect		_VECTOR(26)
 #define SIG_USART0_DATA			_VECTOR(26)
 
 /* USART0, Tx Complete */
+#define USART0_TX_vect_num 			27
 #define USART0_TX_vect			_VECTOR(27)
 #define SIG_USART0_TRANS		_VECTOR(27)
 
 /* Analog Comparator */
+#define ANALOG_COMP_vect_num 		28
 #define ANALOG_COMP_vect		_VECTOR(28)
 #define SIG_COMPARATOR			_VECTOR(28)
 
 /* ADC Conversion Complete */
+#define ADC_vect_num 			29
 #define ADC_vect			_VECTOR(29)
 #define SIG_ADC				_VECTOR(29)
 
 /* EEPROM Ready */
+#define EE_READY_vect_num 			30
 #define EE_READY_vect			_VECTOR(30)
 #define SIG_EEPROM_READY		_VECTOR(30)
 
 /* Timer/Counter3 Capture Event */
+#define TIMER3_CAPT_vect_num 		31
 #define TIMER3_CAPT_vect		_VECTOR(31)
 #define SIG_INPUT_CAPTURE3		_VECTOR(31)
 
 /* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPA_vect_num 		32
 #define TIMER3_COMPA_vect		_VECTOR(32)
 #define SIG_OUTPUT_COMPARE3A		_VECTOR(32)
 
 /* Timer/Counter3 Compare Match B */
+#define TIMER3_COMPB_vect_num 		33
 #define TIMER3_COMPB_vect		_VECTOR(33)
 #define SIG_OUTPUT_COMPARE3B		_VECTOR(33)
 
 /* Timer/Counter3 Compare Match C */
+#define TIMER3_COMPC_vect_num 		34
 #define TIMER3_COMPC_vect		_VECTOR(34)
 #define SIG_OUTPUT_COMPARE3C		_VECTOR(34)
 
 /* Timer/Counter3 Overflow */
+#define TIMER3_OVF_vect_num 			35
 #define TIMER3_OVF_vect			_VECTOR(35)
 #define SIG_OVERFLOW3			_VECTOR(35)
 
 /* USART1, Rx Complete */
+#define USART1_RX_vect_num 			36
 #define USART1_RX_vect			_VECTOR(36)
 #define SIG_USART1_RECV			_VECTOR(36)
 
 /* USART1 Data register Empty */
+#define USART1_UDRE_vect_num 		37
 #define USART1_UDRE_vect		_VECTOR(37)
 #define SIG_USART1_DATA			_VECTOR(37)
 
 /* USART1, Tx Complete */
+#define USART1_TX_vect_num 			38
 #define USART1_TX_vect			_VECTOR(38)
 #define SIG_USART1_TRANS		_VECTOR(38)
 
 /* 2-wire Serial Interface */
+#define TWI_vect_num 			39
 #define TWI_vect			_VECTOR(39)
 #define SIG_2WIRE_SERIAL		_VECTOR(39)
 
 /* Store Program Memory Read */
+#define SPM_READY_vect_num 			40
 #define SPM_READY_vect			_VECTOR(40)
 #define SIG_SPM_READY			_VECTOR(40)
 
 #if defined(__ATmegaxx0__)
 /* Timer/Counter4 Capture Event */
+#define TIMER4_CAPT_vect_num 		41
 #define TIMER4_CAPT_vect		_VECTOR(41)
 #define SIG_INPUT_CAPTURE4		_VECTOR(41)
 
 #endif /* __ATmegaxx0__ */
 
 /* Timer/Counter4 Compare Match A */
+#define TIMER4_COMPA_vect_num 		42
 #define TIMER4_COMPA_vect		_VECTOR(42)
 #define SIG_OUTPUT_COMPARE4A		_VECTOR(42)
 
 /* Timer/Counter4 Compare Match B */
+#define TIMER4_COMPB_vect_num 		43
 #define TIMER4_COMPB_vect		_VECTOR(43)
 #define SIG_OUTPUT_COMPARE4B		_VECTOR(43)
 
 /* Timer/Counter4 Compare Match C */
+#define TIMER4_COMPC_vect_num 		44
 #define TIMER4_COMPC_vect		_VECTOR(44)
 #define SIG_OUTPUT_COMPARE4C		_VECTOR(44)
 
 /* Timer/Counter4 Overflow */
+#define TIMER4_OVF_vect_num 			45
 #define TIMER4_OVF_vect			_VECTOR(45)
 #define SIG_OVERFLOW4			_VECTOR(45)
 
 #if defined(__ATmegaxx0__)
 /* Timer/Counter5 Capture Event */
+#define TIMER5_CAPT_vect_num 		46
 #define TIMER5_CAPT_vect		_VECTOR(46)
 #define SIG_INPUT_CAPTURE5		_VECTOR(46)
 
 #endif /* __ATmegaxx0__ */
 
 /* Timer/Counter5 Compare Match A */
+#define TIMER5_COMPA_vect_num 		47
 #define TIMER5_COMPA_vect		_VECTOR(47)
 #define SIG_OUTPUT_COMPARE5A		_VECTOR(47)
 
 /* Timer/Counter5 Compare Match B */
+#define TIMER5_COMPB_vect_num 		48
 #define TIMER5_COMPB_vect		_VECTOR(48)
 #define SIG_OUTPUT_COMPARE5B		_VECTOR(48)
 
 /* Timer/Counter5 Compare Match C */
+#define TIMER5_COMPC_vect_num 		49
 #define TIMER5_COMPC_vect		_VECTOR(49)
 #define SIG_OUTPUT_COMPARE5C		_VECTOR(49)
 
 /* Timer/Counter5 Overflow */
+#define TIMER5_OVF_vect_num 			50
 #define TIMER5_OVF_vect			_VECTOR(50)
 #define SIG_OVERFLOW5			_VECTOR(50)
 
@@ -1515,26 +1566,32 @@
 #else
 
 /* USART2, Rx Complete */
+#define USART2_RX_vect_num 			51
 #define USART2_RX_vect			_VECTOR(51)
 #define SIG_USART2_RECV			_VECTOR(51)
 
 /* USART2 Data register Empty */
+#define USART2_UDRE_vect_num 		52
 #define USART2_UDRE_vect		_VECTOR(52)
 #define SIG_USART2_DATA			_VECTOR(52)
 
 /* USART2, Tx Complete */
+#define USART2_TX_vect_num 			53
 #define USART2_TX_vect			_VECTOR(53)
 #define SIG_USART2_TRANS		_VECTOR(53)
 
 /* USART3, Rx Complete */
+#define USART3_RX_vect_num 			54
 #define USART3_RX_vect			_VECTOR(54)
 #define SIG_USART3_RECV			_VECTOR(54)
 
 /* USART3 Data register Empty */
+#define USART3_UDRE_vect_num 		55
 #define USART3_UDRE_vect		_VECTOR(55)
 #define SIG_USART3_DATA			_VECTOR(55)
 
 /* USART3, Tx Complete */
+#define USART3_TX_vect_num 			56
 #define USART3_TX_vect			_VECTOR(56)
 #define SIG_USART3_TRANS		_VECTOR(56)
 
@@ -1542,6 +1599,576 @@
 
 #endif /* __ATmegaxx1__ */
 
+/* Device Pin Definitions */
+#define AD0_DDR  	DDRA
+#define AD0_PORT 	PORTA
+#define AD0_PIN  	PINA
+#define AD0_BIT  	0
+
+#define AD1_DDR  	DDRA
+#define AD1_PORT 	PORTA
+#define AD1_PIN  	PINA
+#define AD1_BIT  	1
+
+#define AD2_DDR  	DDRA
+#define AD2_PORT 	PORTA
+#define AD2_PIN  	PINA
+#define AD2_BIT  	2
+
+#define AD3_DDR  	DDRA
+#define AD3_PORT 	PORTA
+#define AD3_PIN  	PINA
+#define AD3_BIT  	3
+
+#define AD4_DDR  	DDRA
+#define AD4_PORT 	PORTA
+#define AD4_PIN  	PINA
+#define AD4_BIT  	4
+
+#define AD5_DDR  	DDRA
+#define AD5_PORT 	PORTA
+#define AD5_PIN  	PINA
+#define AD5_BIT  	5
+
+#define AD6_DDR  	DDRA
+#define AD6_PORT 	PORTA
+#define AD6_PIN  	PINA
+#define AD6_BIT  	6
+
+#define AD7_DDR  	DDRA
+#define AD7_PORT 	PORTA
+#define AD7_PIN  	PINA
+#define AD7_BIT  	7
+
+#define SS_DDR  	DDRB
+#define SS_PORT 	PORTB
+#define SS_PIN  	PINB
+#define SS_BIT  	0
+
+#define PCINT0_DDR  	DDRB
+#define PCINT0_PORT 	PORTB
+#define PCINT0_PIN  	PINB
+#define PCINT0_BIT  	0
+
+#define SCK_DDR  	DDRB
+#define SCK_PORT 	PORTB
+#define SCK_PIN  	PINB
+#define SCK_BIT  	1
+
+#define PCINT1_DDR  	DDRB
+#define PCINT1_PORT 	PORTB
+#define PCINT1_PIN  	PINB
+#define PCINT1_BIT  	1
+
+#define MOSI_DDR  	DDRB
+#define MOSI_PORT 	PORTB
+#define MOSI_PIN  	PINB
+#define MOSI_BIT  	2
+
+#define PCINT2_DDR  	DDRB
+#define PCINT2_PORT 	PORTB
+#define PCINT2_PIN  	PINB
+#define PCINT2_BIT  	2
+
+#define MISO_DDR  	DDRB
+#define MISO_PORT 	PORTB
+#define MISO_PIN  	PINB
+#define MISO_BIT  	3
+
+#define PCINT3_DDR  	DDRB
+#define PCINT3_PORT 	PORTB
+#define PCINT3_PIN  	PINB
+#define PCINT3_BIT  	3
+
+#define OC2A_DDR  	DDRB
+#define OC2A_PORT 	PORTB
+#define OC2A_PIN  	PINB
+#define OC2A_BIT  	4
+
+#define PCINT4_DDR  	DDRB
+#define PCINT4_PORT 	PORTB
+#define PCINT4_PIN  	PINB
+#define PCINT4_BIT  	4
+
+#define OC1A_DDR  	DDRB
+#define OC1A_PORT 	PORTB
+#define OC1A_PIN  	PINB
+#define OC1A_BIT  	5
+
+#define PCINT5_DDR  	DDRB
+#define PCINT5_PORT 	PORTB
+#define PCINT5_PIN  	PINB
+#define PCINT5_BIT  	5
+
+#define OC1B_DDR  	DDRB
+#define OC1B_PORT 	PORTB
+#define OC1B_PIN  	PINB
+#define OC1B_BIT  	6
+
+#define PCINT6_DDR  	DDRB
+#define PCINT6_PORT 	PORTB
+#define PCINT6_PIN  	PINB
+#define PCINT6_BIT  	6
+
+#define OC0A_DDR  	DDRB
+#define OC0A_PORT 	PORTB
+#define OC0A_PIN  	PINB
+#define OC0A_BIT  	7
+
+#define OC1C_DDR  	DDRB
+#define OC1C_PORT 	PORTB
+#define OC1C_PIN  	PINB
+#define OC1C_BIT  	7
+
+#define PCINT7_DDR  	DDRB
+#define PCINT7_PORT 	PORTB
+#define PCINT7_PIN  	PINB
+#define PCINT7_BIT  	7
+
+#define A8_DDR  	DDRC
+#define A8_PORT 	PORTC
+#define A8_PIN  	PINC
+#define A8_BIT  	0
+
+#define A9_DDR  	DDRC
+#define A9_PORT 	PORTC
+#define A9_PIN  	PINC
+#define A9_BIT  	1
+
+#define A10_DDR  	DDRC
+#define A10_PORT 	PORTC
+#define A10_PIN  	PINC
+#define A10_BIT  	2
+
+#define A11_DDR  	DDRC
+#define A11_PORT 	PORTC
+#define A11_PIN  	PINC
+#define A11_BIT  	3
+
+#define A12_DDR  	DDRC
+#define A12_PORT 	PORTC
+#define A12_PIN  	PINC
+#define A12_BIT  	4
+
+#define A13_DDR  	DDRC
+#define A13_PORT 	PORTC
+#define A13_PIN  	PINC
+#define A13_BIT  	5
+
+#define A14_DDR  	DDRC
+#define A14_PORT 	PORTC
+#define A14_PIN  	PINC
+#define A14_BIT  	6
+
+#define A15_DDR  	DDRC
+#define A15_PORT 	PORTC
+#define A15_PIN  	PINC
+#define A15_BIT  	7
+
+#define SCL_DDR  	DDRD
+#define SCL_PORT 	PORTD
+#define SCL_PIN  	PIND
+#define SCL_BIT  	0
+
+#define INT0_DDR  	DDRD
+#define INT0_PORT 	PORTD
+#define INT0_PIN  	PIND
+#define INT0_BIT  	0
+
+#define SDA_DDR  	DDRD
+#define SDA_PORT 	PORTD
+#define SDA_PIN  	PIND
+#define SDA_BIT  	1
+
+#define INT1_DDR  	DDRD
+#define INT1_PORT 	PORTD
+#define INT1_PIN  	PIND
+#define INT1_BIT  	1
+
+#define RXD1_DDR  	DDRD
+#define RXD1_PORT 	PORTD
+#define RXD1_PIN  	PIND
+#define RXD1_BIT  	2
+
+#define INT2_DDR  	DDRD
+#define INT2_PORT 	PORTD
+#define INT2_PIN  	PIND
+#define INT2_BIT  	2
+
+#define TXD1_DDR  	DDRD
+#define TXD1_PORT 	PORTD
+#define TXD1_PIN  	PIND
+#define TXD1_BIT  	3
+
+#define INT3_DDR  	DDRD
+#define INT3_PORT 	PORTD
+#define INT3_PIN  	PIND
+#define INT3_BIT  	3
+
+#define ICP1_DDR  	DDRD
+#define ICP1_PORT 	PORTD
+#define ICP1_PIN  	PIND
+#define ICP1_BIT  	4
+
+#define XCK1_DDR  	DDRD
+#define XCK1_PORT 	PORTD
+#define XCK1_PIN  	PIND
+#define XCK1_BIT  	5
+
+#define T1_DDR  	DDRD
+#define T1_PORT 	PORTD
+#define T1_PIN  	PIND
+#define T1_BIT  	6
+
+#define T0_DDR  	DDRD
+#define T0_PORT 	PORTD
+#define T0_PIN  	PIND
+#define T0_BIT  	7
+
+#define RXD0_DDR  	DDRE
+#define RXD0_PORT 	PORTE
+#define RXD0_PIN  	PINE
+#define RXD0_BIT  	0
+
+#define PCINT8_DDR  	DDRE
+#define PCINT8_PORT 	PORTE
+#define PCINT8_PIN  	PINE
+#define PCINT8_BIT  	0
+
+#define TXD0_DDR  	DDRE
+#define TXD0_PORT 	PORTE
+#define TXD0_PIN  	PINE
+#define TXD0_BIT  	1
+
+#define XCK0_DDR  	DDRE
+#define XCK0_PORT 	PORTE
+#define XCK0_PIN  	PINE
+#define XCK0_BIT  	2
+
+#define AIN0_DDR  	DDRE
+#define AIN0_PORT 	PORTE
+#define AIN0_PIN  	PINE
+#define AIN0_BIT  	2
+
+#define OC3A_DDR  	DDRE
+#define OC3A_PORT 	PORTE
+#define OC3A_PIN  	PINE
+#define OC3A_BIT  	3
+
+#define AIN1_DDR  	DDRE
+#define AIN1_PORT 	PORTE
+#define AIN1_PIN  	PINE
+#define AIN1_BIT  	3
+
+#define OC3B_DDR  	DDRE
+#define OC3B_PORT 	PORTE
+#define OC3B_PIN  	PINE
+#define OC3B_BIT  	4
+
+#define INT4_DDR  	DDRE
+#define INT4_PORT 	PORTE
+#define INT4_PIN  	PINE
+#define INT4_BIT  	4
+
+#define OC3C_DDR  	DDRE
+#define OC3C_PORT 	PORTE
+#define OC3C_PIN  	PINE
+#define OC3C_BIT  	5
+
+#define INT5_DDR  	DDRE
+#define INT5_PORT 	PORTE
+#define INT5_PIN  	PINE
+#define INT5_BIT  	5
+
+#define T3_DDR  	DDRE
+#define T3_PORT 	PORTE
+#define T3_PIN  	PINE
+#define T3_BIT  	6
+
+#define INT6_DDR  	DDRE
+#define INT6_PORT 	PORTE
+#define INT6_PIN  	PINE
+#define INT6_BIT  	6
+
+#define CLKO_DDR  	DDRE
+#define CLKO_PORT 	PORTE
+#define CLKO_PIN  	PINE
+#define CLKO_BIT  	7
+
+#define ICP3_DDR  	DDRE
+#define ICP3_PORT 	PORTE
+#define ICP3_PIN  	PINE
+#define ICP3_BIT  	7
+
+#define INT7_DDR  	DDRE
+#define INT7_PORT 	PORTE
+#define INT7_PIN  	PINE
+#define INT7_BIT  	7
+
+#define ADC0_DDR  	DDRF
+#define ADC0_PORT 	PORTF
+#define ADC0_PIN  	PINF
+#define ADC0_BIT  	0
+
+#define ADC1_DDR  	DDRF
+#define ADC1_PORT 	PORTF
+#define ADC1_PIN  	PINF
+#define ADC1_BIT  	1
+
+#define ADC2_DDR  	DDRF
+#define ADC2_PORT 	PORTF
+#define ADC2_PIN  	PINF
+#define ADC2_BIT  	2
+
+#define ADC3_DDR  	DDRF
+#define ADC3_PORT 	PORTF
+#define ADC3_PIN  	PINF
+#define ADC3_BIT  	3
+
+#define ADC4_DDR  	DDRF
+#define ADC4_PORT 	PORTF
+#define ADC4_PIN  	PINF
+#define ADC4_BIT  	4
+
+#define ADC5_DDR  	DDRF
+#define ADC5_PORT 	PORTF
+#define ADC5_PIN  	PINF
+#define ADC5_BIT  	5
+
+#define ADC6_DDR  	DDRF
+#define ADC6_PORT 	PORTF
+#define ADC6_PIN  	PINF
+#define ADC6_BIT  	6
+
+#define ADC7_DDR  	DDRF
+#define ADC7_PORT 	PORTF
+#define ADC7_PIN  	PINF
+#define ADC7_BIT  	7
+
+#define WR_DDR  	DDRG
+#define WR_PORT 	PORTG
+#define WR_PIN  	PING
+#define WR_BIT  	0
+
+#define RD_DDR  	DDRG
+#define RD_PORT 	PORTG
+#define RD_PIN  	PING
+#define RD_BIT  	1
+
+#define ALE_DDR  	DDRG
+#define ALE_PORT 	PORTG
+#define ALE_PIN  	PING
+#define ALE_BIT  	2
+
+#define OC0B_DDR  	DDRG
+#define OC0B_PORT 	PORTG
+#define OC0B_PIN  	PING
+#define OC0B_BIT  	5
+
+#if defined(__ATmegaxx0__)
+
+#define RXD2_DDR  	DDRH
+#define RXD2_PORT 	PORTH
+#define RXD2_PIN  	PINH
+#define RXD2_BIT  	0
+
+#define TXD2_DDR  	DDRH
+#define TXD2_PORT 	PORTH
+#define TXD2_PIN  	PINH
+#define TXD2_BIT  	1
+
+#define XCK2_DDR  	DDRH
+#define XCK2_PORT 	PORTH
+#define XCK2_PIN  	PINH
+#define XCK2_BIT  	2
+
+#define OC4A_DDR  	DDRH
+#define OC4A_PORT 	PORTH
+#define OC4A_PIN  	PINH
+#define OC4A_BIT  	3
+
+#define OC4B_DDR  	DDRH
+#define OC4B_PORT 	PORTH
+#define OC4B_PIN  	PINH
+#define OC4B_BIT  	4
+
+#define OC4C_DDR  	DDRH
+#define OC4C_PORT 	PORTH
+#define OC4C_PIN  	PINH
+#define OC4C_BIT  	5
+
+#define OC2B_DDR  	DDRH
+#define OC2B_PORT 	PORTH
+#define OC2B_PIN  	PINH
+#define OC2B_BIT  	6
+
+#define T4_DDR  	DDRH
+#define T4_PORT 	PORTH
+#define T4_PIN  	PINH
+#define T4_BIT  	7
+
+#define RXD3_DDR  	DDRJ
+#define RXD3_PORT 	PORTJ
+#define RXD3_PIN  	PINJ
+#define RXD3_BIT  	0
+
+#define PCINT9_DDR  	DDRJ
+#define PCINT9_PORT 	PORTJ
+#define PCINT9_PIN  	PINJ
+#define PCINT9_BIT  	0
+
+#define TXD3_DDR  	DDRJ
+#define TXD3_PORT 	PORTJ
+#define TXD3_PIN  	PINJ
+#define TXD3_BIT  	1
+
+#define PCINT10_DDR  	DDRJ
+#define PCINT10_PORT 	PORTJ
+#define PCINT10_PIN  	PINJ
+#define PCINT10_BIT  	1
+
+#define XCK3_DDR  	DDRJ
+#define XCK3_PORT 	PORTJ
+#define XCK3_PIN  	PINJ
+#define XCK3_BIT  	2
+
+#define PCINT11_DDR  	DDRJ
+#define PCINT11_PORT 	PORTJ
+#define PCINT11_PIN  	PINJ
+#define PCINT11_BIT  	2
+
+#define PCINT12_DDR  	DDRJ
+#define PCINT12_PORT 	PORTJ
+#define PCINT12_PIN  	PINJ
+#define PCINT12_BIT  	3
+
+#define PCINT13_DDR  	DDRJ
+#define PCINT13_PORT 	PORTJ
+#define PCINT13_PIN  	PINJ
+#define PCINT13_BIT  	4
+
+#define PCINT14_DDR  	DDRJ
+#define PCINT14_PORT 	PORTJ
+#define PCINT14_PIN  	PINJ
+#define PCINT14_BIT  	5
+
+#define PCINT15_DDR  	DDRJ
+#define PCINT15_PORT 	PORTJ
+#define PCINT15_PIN  	PINJ
+#define PCINT15_BIT  	6
+
+#define ADC8_DDR  	DDRK
+#define ADC8_PORT 	PORTK
+#define ADC8_PIN  	PINK
+#define ADC8_BIT  	0
+
+#define PCINT16_DDR  	DDRK
+#define PCINT16_PORT 	PORTK
+#define PCINT16_PIN  	PINK
+#define PCINT16_BIT  	0
+
+#define ADC9_DDR  	DDRK
+#define ADC9_PORT 	PORTK
+#define ADC9_PIN  	PINK
+#define ADC9_BIT  	1
+
+#define PCINT17_DDR  	DDRK
+#define PCINT17_PORT 	PORTK
+#define PCINT17_PIN  	PINK
+#define PCINT17_BIT  	1
+
+#define ADC10_DDR  	DDRK
+#define ADC10_PORT 	PORTK
+#define ADC10_PIN  	PINK
+#define ADC10_BIT  	2
+
+#define PCINT18_DDR  	DDRK
+#define PCINT18_PORT 	PORTK
+#define PCINT18_PIN  	PINK
+#define PCINT18_BIT  	2
+
+#define ADC11_DDR  	DDRK
+#define ADC11_PORT 	PORTK
+#define ADC11_PIN  	PINK
+#define ADC11_BIT  	3
+
+#define PCINT19_DDR  	DDRK
+#define PCINT19_PORT 	PORTK
+#define PCINT19_PIN  	PINK
+#define PCINT19_BIT  	3
+
+#define ADC12_DDR  	DDRK
+#define ADC12_PORT 	PORTK
+#define ADC12_PIN  	PINK
+#define ADC12_BIT  	4
+
+#define PCINT20_DDR  	DDRK
+#define PCINT20_PORT 	PORTK
+#define PCINT20_PIN  	PINK
+#define PCINT20_BIT  	4
+
+#define ADC13_DDR  	DDRK
+#define ADC13_PORT 	PORTK
+#define ADC13_PIN  	PINK
+#define ADC13_BIT  	5
+
+#define PCINT21_DDR  	DDRK
+#define PCINT21_PORT 	PORTK
+#define PCINT21_PIN  	PINK
+#define PCINT21_BIT  	5
+
+#define ADC14_DDR  	DDRK
+#define ADC14_PORT 	PORTK
+#define ADC14_PIN  	PINK
+#define ADC14_BIT  	6
+
+#define PCINT22_DDR  	DDRK
+#define PCINT22_PORT 	PORTK
+#define PCINT22_PIN  	PINK
+#define PCINT22_BIT  	6
+
+#define ADC15_DDR  	DDRK
+#define ADC15_PORT 	PORTK
+#define ADC15_PIN  	PINK
+#define ADC15_BIT  	7
+
+#define PCINT23_DDR  	DDRK
+#define PCINT23_PORT 	PORTK
+#define PCINT23_PIN  	PINK
+#define PCINT23_BIT  	7
+
+#define ICP4_DDR  	DDRL
+#define ICP4_PORT 	PORTL
+#define ICP4_PIN  	PINL
+#define ICP4_BIT  	0
+
+#define ICP5_DDR  	DDRL
+#define ICP5_PORT 	PORTL
+#define ICP5_PIN  	PINL
+#define ICP5_BIT  	1
+
+#define T5_DDR  	DDRL
+#define T5_PORT 	PORTL
+#define T5_PIN  	PINL
+#define T5_BIT  	2
+
+#define OC5A_DDR  	DDRL
+#define OC5A_PORT 	PORTL
+#define OC5A_PIN  	PINL
+#define OC5A_BIT  	3
+
+#define OC5B_DDR  	DDRL
+#define OC5B_PORT 	PORTL
+#define OC5B_PIN  	PINL
+#define OC5B_BIT  	4
+
+#define OC5C_DDR  	DDRL
+#define OC5C_PORT 	PORTL
+#define OC5C_PIN  	PINL
+#define OC5C_BIT  	5
+
+#endif /* __ATmegaxx0__ */
+
 #if defined(__ATmegaxx0__)
 # undef __ATmegaxx0__
 #endif
