Index: src/Makefile.am =================================================================== RCS file: /sources/simulavr/simulavr/src/Makefile.am,v retrieving revision 1.27 diff -u -r1.27 Makefile.am --- src/Makefile.am 16 Apr 2004 04:33:51 -0000 1.27 +++ src/Makefile.am 21 Jan 2006 20:44:47 -0000 @@ -91,6 +91,7 @@ defn/90s8515.h \ defn/mega8.h \ defn/mega16.h \ + defn/mega32.h \ defn/mega103.h \ defn/mega128.h \ defn/43usb320.h \ Index: src/devsupp.c =================================================================== RCS file: /sources/simulavr/simulavr/src/devsupp.c,v retrieving revision 1.28 diff -u -r1.28 devsupp.c --- src/devsupp.c 26 Feb 2004 07:22:15 -0000 1.28 +++ src/devsupp.c 21 Jan 2006 20:44:48 -0000 @@ -81,6 +81,7 @@ VTAB_AT90S4414, VTAB_ATMEGA8, VTAB_ATMEGA16, + VTAB_ATMEGA32, VTAB_ATMEGA103, VTAB_ATMEGA128, VTAB_AT43USB355, @@ -213,6 +214,7 @@ #include "defn/mega8.h" #include "defn/mega16.h" +#include "defn/mega32.h" #include "defn/mega103.h" #include "defn/mega128.h" @@ -235,6 +237,7 @@ &defn_at90s8515, &defn_atmega8, &defn_atmega16, + &defn_atmega32, &defn_atmega103, &defn_atmega128, &defn_at43usb351, Index: src/intvects.c =================================================================== RCS file: /sources/simulavr/simulavr/src/intvects.c,v retrieving revision 1.17 diff -u -r1.17 intvects.c --- src/intvects.c 26 Feb 2004 07:22:15 -0000 1.17 +++ src/intvects.c 21 Jan 2006 20:44:49 -0000 @@ -219,6 +219,56 @@ 0x28, 0x00, { 0x57, 1<<7 }, NO_BIT } }; +/* + * Vector Table for devices: + * atmega32 + */ + +static IntVectTable vtab_atmega32 = { + .RESET = { "IRQ_RESET", + 0x00, 0x00, NO_BIT, NO_BIT }, + .INT0 = { "IRQ_INT0", + 0x02, 0x00, { 0x5b, 1<<6 }, { 0x5a, 1<<6 } }, + .INT1 = { "IRQ_INT1", + 0x04, 0x00, { 0x5b, 1<<7 }, { 0x5a, 1<<7 } }, + .TIMER2_COMP = { "IRQ_TIMER2_COMP", + 0x06, 0x00, { 0x59, 1<<7 }, { 0x58, 1<<7 } }, + .TIMER2_OVF = { "IRQ_TIMER2_OVF", + 0x08, 0x00, { 0x59, 1<<6 }, { 0x58, 1<<6 } }, + .TIMER1_CAPT = { "IRQ_TIMER1_CAPT", + 0x0a, 0x00, { 0x59, 1<<5 }, { 0x58, 1<<5 } }, + .TIMER1_COMPA = { "IRQ_TIMER1_COMPA", + 0x0c, 0x00, { 0x59, 1<<4 }, { 0x58, 1<<4 } }, + .TIMER1_COMPB = { "IRQ_TIMER1_COMPB", + 0x0e, 0x00, { 0x59, 1<<3 }, { 0x58, 1<<3 } }, + .TIMER1_OVF = { "IRQ_TIMER1_OVF", + 0x10, 0x00, { 0x59, 1<<2 }, { 0x58, 1<<2 } }, + .TIMER0_OVF = { "IRQ_TIMER0_OVF", + 0x12, 0x00, { 0x59, 1<<0 }, { 0x58, 1<<0 } }, + .SPI_STC = { "IRQ_SPI_STC", + 0x14, 0x00, { 0x2d, 1<<7 }, NO_BIT }, + .UART_RX = { "IRQ_UART_RX", + 0x16, 0x00, { 0x2a, 1<<7 }, { 0x2b, 1<<7 } }, + .UART_UDRE = { "IRQ_UART_UDRE", + 0x18, 0x00, { 0x2a, 1<<5 }, { 0x2b, 1<<5 } }, + .UART_TX = { "IRQ_UART_TX", + 0x1a, 0x00, { 0x2a, 1<<6 }, { 0x2b, 1<<6 } }, + .ADC = { "IRQ_ADC", + 0x1c, 0x00, { 0x26, 1<<3 }, { 0x26, 1<<4 } }, + .EE_READY = { "IRQ_EE_READY", + 0x1e, 0x00, { 0x3c, 1<<3 }, NO_BIT }, + .ANA_COMP = { "IRQ_ANA_COMP", + 0x20, 0x00, { 0x28, 1<<3 }, { 0x28, 1<<4 } }, + .TWI = { "IRQ_TWI", + 0x22, 0x00, { 0x57, 1<<0 }, { 0x56, 1<<7 } }, + .INT2 = { "IRQ_INT2", + 0x24, 0x00, { 0x5b, 1<<5 }, { 0x5a, 1<<5 } }, + .TIMER0_COMP = { "IRQ_TIMER0_COMP", + 0x26, 0x00, { 0x59, 1<<1 }, { 0x58, 1<<1 } }, + .SPM_READY = { "IRQ_SPM_READY", + 0x28, 0x00, { 0x57, 1<<7 }, NO_BIT } +}; + /* * Vector Table for devices: @@ -468,6 +518,7 @@ &vtab_at90s4414, &vtab_atmega8, &vtab_atmega16, + &vtab_atmega32, &vtab_atmega103, &vtab_atmega128, &vtab_at43usb355, Index: src/disp/disp.c =================================================================== RCS file: /sources/simulavr/simulavr/src/disp/disp.c,v retrieving revision 1.18 diff -u -r1.18 disp.c --- src/disp/disp.c 1 Dec 2003 05:48:34 -0000 1.18 +++ src/disp/disp.c 21 Jan 2006 20:44:51 -0000 @@ -815,7 +815,7 @@ } if ((val >= 26) && (val <= 31)) { - unsigned int areg; + unsigned int areg=0; switch (val) { case 26: Index: .project =================================================================== RCS file: .project diff -N .project --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ .project 1 Jan 1970 00:00:00 -0000 @@ -0,0 +1,11 @@ + + + simulavr + + + + + + + + Index: src/defn/mega32.h =================================================================== RCS file: src/defn/mega32.h diff -N src/defn/mega32.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ src/defn/mega32.h 1 Jan 1970 00:00:00 -0000 @@ -0,0 +1,213 @@ +/* + * $Id: mega32.h,v 1.1 2006/01/21 20:23:00 troth Exp $ + * + **************************************************************************** + * + * simulavr - A simulator for the Atmel AVR family of microcontrollers. + * Copyright (C) 2004 Theodore A. Roth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + **************************************************************************** + */ + +#if defined (IN_DEVSUPP_C) +/* *INDENT-OFF* */ + +static DevSuppDefn defn_atmega32 = { + .name = "atmega32", + .stack_type = STACK_MEMORY, + .irq_vect_idx = VTAB_ATMEGA32, + + .size = { + .pc = 2, + .stack = 0, + .flash = 32 * 1024, + .sram = 2 * 1024, + .eeprom = 1024 + }, + + .io_reg = { + { .addr = 0x20, .name = "TWBR", }, + { .addr = 0x21, .name = "TWSR", }, + { .addr = 0x22, .name = "TWAR", }, + { .addr = 0x23, .name = "TWDR", }, + { .addr = 0x24, .name = "ADCL", }, + { .addr = 0x25, .name = "ADCH", }, + { .addr = 0x26, .name = "ADCSRA", }, + { .addr = 0x27, .name = "ADMUX", }, + { .addr = 0x28, .name = "ACSR", }, + { .addr = 0x29, .name = "UBRRL", }, + { .addr = 0x2a, .name = "UCSRB", }, + { .addr = 0x2b, .name = "UCSRA", }, + { .addr = 0x2c, .name = "UDR", }, + { .addr = 0x2d, .name = "SPCR", }, + { .addr = 0x2e, .name = "SPSR", }, + { .addr = 0x2f, .name = "SPDR", }, + { + .addr = 0x30, + .name = "PIND", + .vdev_create = port_create, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x31, + .name = "DDRD", + .ref_addr = 0x30, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x32, + .name = "PORTD", + .ref_addr = 0x30, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x33, + .name = "PINC", + .vdev_create = port_create, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x34, + .name = "DDRC", + .ref_addr = 0x33, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x35, + .name = "PORTC", + .ref_addr = 0x33, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x36, + .name = "PINB", + .vdev_create = port_create, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x37, + .name = "DDRB", + .ref_addr = 0x36, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x38, + .name = "PORTB", + .ref_addr = 0x36, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x39, + .name = "PINA", + .vdev_create = port_create, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x3a, + .name = "DDRA", + .ref_addr = 0x39, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x3b, + .name = "PORTA", + .ref_addr = 0x39, + .reset_value = 0x00, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { .addr = 0x40, .name = "UBRRH", }, + { .addr = 0x41, .name = "WDTCR", }, + { .addr = 0x42, .name = "ASSR", }, + { .addr = 0x43, .name = "OCR2", }, + { .addr = 0x44, .name = "TCNT2", }, + { .addr = 0x45, .name = "TCCR2", }, + { .addr = 0x46, .name = "ICR1L", }, + { .addr = 0x47, .name = "ICR1H", }, + { .addr = 0x48, .name = "OCR1BL", }, + { .addr = 0x49, .name = "OCR1BH", }, + { .addr = 0x4a, .name = "OCR1AL", }, + { .addr = 0x4b, .name = "OCR1AH", }, + { .addr = 0x4c, .name = "TCNT1L", }, + { .addr = 0x4d, .name = "TCNT1H", }, + { .addr = 0x4e, .name = "TCCR1B", }, + { .addr = 0x4f, .name = "TCCR1A", }, + { .addr = 0x50, .name = "SFIOR", }, + { .addr = 0x51, .name = "OCDR", }, + { .addr = 0x52, .name = "TCNT0", }, + { .addr = 0x53, .name = "TCCR0", }, + { .addr = 0x54, .name = "MCUCSR", }, + { .addr = 0x55, .name = "MCUCR", }, + { .addr = 0x56, .name = "TWCR", }, + { .addr = 0x57, .name = "SPMCR", }, + { .addr = 0x58, .name = "TIFR", }, + { .addr = 0x59, .name = "TIMSK", }, + { .addr = 0x5a, .name = "GIFR", }, + { .addr = 0x5b, .name = "GICR", }, + { .addr = 0x5c, .name = "OCR0", }, + { + .addr = 0x5d, + .name = "SPL", + .vdev_create = sp_create, + .reset_value = 0, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x5e, + .name = "SPH", + .ref_addr = 0x5d, + .reset_value = 0, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + { + .addr = 0x5f, + .name = "SREG", + .vdev_create = sreg_create, + .reset_value = 0, + .rd_mask = 0xff, + .wr_mask = 0xff, + }, + IO_REG_DEFN_TERMINATOR + } +}; + +/* *INDENT-ON* */ +#endif /* IN_DEVSUPP_C */